PTP (IEEE 1588)

showstack / protocols / ptp-1588

Also called Precision Time Protocol, IEEE 1588, PTPv2, gPTP.

IEEE 1588 Precision Time Protocol distributes a common clock across an ethernet network to sub-microsecond accuracy by timestamping messages in both directions. It is the timing foundation under AES67, Dante, RAVENNA, ST 2110 and AVB, and when it is unhappy all of them fail at once.

Timecode and syncPaid specIEEEReported

Clock and sync Tiny, ruthlessly regular

Almost no bandwidth. Carries no content at all, only agreement about when. Its value is entirely in its regularity.

What kills it. Jitter, an unaware switch delaying the timestamps it was meant to correct, and two devices both convinced they are the master.

The four flows, and why the model is worth having →

Ports

udp/319 PTP event messages (Sync, Delay_Req, Pdelay_Req, Pdelay_Resp)
These are the timestamped messages. Anything that delays them asymmetrically becomes a clock offset error.

udp/320 PTP general messages (Announce, Follow_Up, Delay_Resp, management)

Multicast

224.0.1.129 (IPv4 PTP primary address)
224.0.0.107 (IPv4 peer delay messages, link-local)
FF0X::181 (IPv6)
Some profiles also use 224.0.1.130 through 224.0.1.132; Audinate and ALC NetworX both document the 224.0.1.129-132 block plus 224.0.0.107 as the addresses to allow through a switch. PTP can also run unicast or over Layer 2 (gPTP) depending on profile.

What goes wrong

Profiles are the trap. Default profile, the AES67 media profile, SMPTE ST 2059-2 and gPTP (802.1AS) are all IEEE 1588. Devices on different profiles, or on the same profile with different domain numbers, will never lock.

Dante's default clock is PTP version 1 (IEEE 1588-2002), not PTPv2. A Dante plant and an AES67 or ST 2110 plant need something that deliberately bridges the two clock domains, not just a patch cable.

The Best Master Clock Algorithm means the grandmaster can change without anyone touching anything. Plug in a device advertising a better clock class and the whole facility re-locks, usually at the worst moment.

Asymmetry is invisible and fatal. Different fibre lengths in each direction, a one-way shaper, or a switch that is transparent-clock aware in one direction only, all produce a constant offset that no log will flag.

A switch that is not PTP aware still passes PTP, it just adds variable queue delay. It will look fine on a quiet network at setup and drift when the show traffic arrives.

UDP 319 and 320 are frequently blocked by default on firewalls and by multicast filtering. Symptoms are audio that works for a few minutes after boot and then falls apart as the local clock walks away.

What speaks PTP (IEEE 1588) (9)

Product	Direction	Notes
Dante Controller Audinate	bidirectional	Displays PTP clock status, master election and offsets.
Dante Domain Manager Audinate	bidirectional	Clock management across domains.
PIXERA AV Stumpfl	bidirectional	For synchronised multi-machine playback.
Q-SYS Designer QSC, LLC	bidirectional	PTPv2 (IEEE 1588-2008) on multicast 224.0.1.129, UDP 319-320. It is the clock for Q-LAN and AES67 and is documented as time-sensitive traffic the network must prioritise.
Cisco Catalyst 9200 Series Cisco	bidirectional	Transparent or boundary clock support varies sharply by model and licence.
Cisco Catalyst 9300 Cisco	bidirectional	Depending on licence and configuration.
DirectOut PRODIGY.MP DirectOut	bidirectional	For AES67 and RAVENNA.
Evertz 5601MSC Master Sync and Clock Evertz	out	PTP grandmaster, depending on option.
Luminex GigaCore 26i Luminex Network Intelligence	bidirectional	Clock distribution.